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1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5516 cs5520 16-bit/20-bit bridge transducer a/d converter features l on-chip instrumentation amplifier l on-chip programmable gain amplifier l on-chip 4-bit d/a for offset removal l dynamic excitation options l linearity error: 0.0015% fs - 20- b it , no missing codes l cmrr at 50/60 hz > 200 db l system calibration capability with calibration read/write option l 3- , 4-, or 5- wire serial communications port l low power consumption: 40 mw - 10 w standby mode for portable applications description the cs5516 and cs5520 are complete solutions for dig- itizing low level signals from strain gauges, load cells, and pressure transducers. any family of mv output transducers, including those requiring bridge excitation, can be interfaced directly to the cs5516 or cs5520. the devices offer an on-chip software programmable instru- mentation amplifier block, choice of dc or ac bridge excitation, and software selectable reference and signal demodulation. the cs5516 uses delta-sigma modulation to achieve 16-bit resolution at output word rates up to 60 sps . the cs5520 achieves 20-bit resolution at output word rates up to 60 sps. the cs5516 and cs5520 sample at a rate set by the user in the form of either an external cmos clock or a crystal. on-chip digital filtering provides rejection of all frequencies above 12 hz for a 4.096 mhz clock. the cs5516 and cs5520 include system calibration to null offset and gain errors in the input channel. the digi- tal values associated with the system calibration can be written to, or read from, the calibration ram locations at any time via the serial communications port. the 4-bit dc offset d/a converter, in conjunction with digital cor- rection, is initially used to zero the input offset value. ordering information see page 29. i $,1 $,1 95() 95() %ulgjh %; ; ; 6\qf *dlq %orfn elw'$ &rqyhuwhu s %; 9$ 9$ $*1' $*1' &kdqqho 'howd6ljpd 0rgxodwru ,1 287 ,1 287 &kdqqho ),5 )lowhu &doleudwlrq 0'59 0'59 9' 9' '*1' ;,1 ;287 602'( 6&/. '5'< &6 567 6huldo,qwhuidfh ? 62' 6,' mar 95 ds74f1 copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cs5516 cs5520 16-bit & 20-bit bridge transducer a/d converters sep ?05 ds74f2
cs5516 analog characteristics (t a = t min to t max ; va+, vd+, mdrv+ = 5v; va-, vd- = -5v; vref= 2.5v(external differential voltage across vref+ and vref-); f clk = 4.9152 mhz; ac excitation 300 hz; gain = 25; bipolar mode; r source = 300 w with a 4.7nf to agnd at ain (see note 1); unless otherwise specified.) parameter* min typ max units specified temperature range -40 to +85 c accuracy linearity error - 0.0015 0.003 %fs differential nonlinearity - 0.25 0.5 lsb 16 unipolar gain error (note 2) - 8 31 ppm bipolar gain error (note 2) - 8 31 ppm unipolar/bipolar gain drift - 1 - ppm/ c unipolar offset (note 2) - 1 2 lsb 16 bipolar offset (note 2) - 1 2 lsb 16 offset drift - 0.005 - m v/ c noise (referred to input) gain = 25 (25 x 1) gain = 50 (25 x 2) gain = 100 (25 x 4) gain = 200 (25 x 8) - - - - 250 200 150 150 - - - - nvrms nvrms nvrms nvrms notes: 1. the ain and vref pins present a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. both source resistance and shunt capacitance are therefore critical in determining the source impedance requirements of the cs5516 and cs5520 at these pins. 2. applies after system calibration at the temperature of interest. specifications are subject to change without notice. unipolar mode bipolar mode m v lsbs % fs ppm fs lsbs % fs ppm fs 0.4 0.26 0.0004 4 0.13 0.0002 2 0.76 0.50 0.0008 8 0.26 0.0004 4 1.52 1.00 0.0015 15 0.50 0.0008 8 3.04 2.00 0.0030 30 1.00 0.0015 15 6.08 4.00 0.0061 61 2.00 0.0030 30 vref = 2.5v pga gain = 1 cs5516; 16-bit unit conversion factors * refer to the specification definitions immediately following the pin description section. 2 ds74f1 2 ds74f2
cs5520 unipolar mode bipolar mode m v lsbs % fs ppm fs lsbs % fs ppm fs 0.025 0.26 0.0000238 0.25 0.13 0.0000119 0.125 0.047 0.50 0.0000477 0.50 0.26 0.0000238 0.25 0.095 1.00 0.0000954 1.0 0.50 0.0000477 0.50 0.190 2.00 0.0001907 2.0 1.00 0.0000954 1.0 0.380 4.00 0.0003814 4.0 2.00 0.0001907 2.0 vref = 2.5v pga gain = 1 cs5520; 20-bit unit conversion factors specifications are subject to change without notice. * refer to the specification definitions immediately following the pin description section. analog characteristics (continued) parameter* min typ max units specified temperature range -40 to +85 c accuracy linearity error - 0.0007 0.0015 %fs differential nonlinearity (no missing codes) 20 - - bits unipolar gain error (note 2) - 4 24 ppm bipolar gain error (note 2) - 4 24 ppm unipolar/bipolar gain drift - 1 - ppm/ c unipolar offset (note 2) - 4 8 lsb 20 bipolar offset (note 2) - 4 8 lsb 20 offset drift - 0.005 - m v/ c noise (referred to input) gain = 25 (25 x 1) gain = 50 (25 x 2) gain = 100 (25 x 4) gain = 200 (25 x 8) - - - - 250 200 150 150 - - - - nvrms nvrms nvrms nvrms ds74f1 3 ds74f2 3
analog characteristics (continued) parameter min typ max units specified temperature range -40 to +85 c analog input analog input range unipolar bipolar 12.5, 25, 50, 100 12.5, 25, 50, 100 mv mv common mode rejection dc 50, 60 hz - - 165 200 - - db db input capacitance - 5 - pf input bias current (note 1) - 100 - pa instrumentation amplifier gain - 25 - bandwidth - 200 - khz unity gain bandwidth - 5 - mhz output slew rate - 1.5 - v/ m sec noise @ 10 hz bw - 100 - nvrms power supply rejection @ 50/60 hz (note 3) - 120 - db common mode range (note 4) - 3 -v chopping frequency - xin/128 - hz programmable gain amplifier gain tracking (note 5) - 1 -% 4-bit offset trim dac accuracy - 5 -% voltage reference input range (note 6) 2.0 2.5 3.8 v common mode rejection: dc 50, 60 hz - - 60 200 - - db input capacitance - 15 - pf input bias current (note 1) - 10 - na notes: 3. this includes the on-chip digital filtering. 4. the maximum magnitude of the differential input voltage, vdiff(in) is determined by the following: vdiff(in) < 300 mv - |vcm/12.5 | and should never exceed 300mv. vcm is the common mode voltage which is applied to the instrumentation amplifier inputs. the above equation should be used to calculate the allowable common mode voltage for a given differential voltage applied to the first gain stage inputs. this limit ensures that the instrumentation amplifier does not saturate. 5. gain tracking accuracy can be significantly improved by uploading a calibrated gain word to the gain register for each pga gain selection. 6. the common mode voltage on the voltage reference input, plus the reference range, [(vref+) - (vref-)]/2, must not exceed 3 volts. cs5516, cs5520 4 ds74f1 4 ds74f2
analog characteristics (continued) parameter min typ max units modulator differential voltage reference nominal output voltage - 3.75 - v initial output voltage tolerance - 100 -mv temperature coefficient - 100 - ppm/ c line regulation (4.75v < va < 5.25v) - 0.5 - mv/v output voltage noise 0.1 to 15 hz - 10 - m v p-p output current drive: source current sink current - - - - 20 20 m a m a power supplies dc power supply currents i a+ i a- i d+ i d- - - - - 2.7 -2.7 1.5 -0.6 3.5 -3.5 2.2 -0.8 ma ma ma ma power dissipation: (note 7) normal operation standby mode - - 37.5 10 - - mw m w power supply rejection: dc positive supplies dc negative supplies - - 100 95 - - db db system calibration specifications positive full scale calibration range (note 8) unipolar mode bipolar mode 0.8t 0.8t - - 1.2t 1.2t v v maximum ratiometric offset calibration range (note 8) unipolar mode bipolar mode -2t -2t - - +2t +2t v v differential input voltage range (notes 4, 8, 9, 10) unipolar mode bipolar voffset + (1.2t) voffset (1.2t) v v notes: 7. all outputs unloaded. all inputs cmos levels. 8. t=vref/(gx25), where t is the full scale span, where vref is the differential voltage across vref+ and vref- in volts, and g is the gain setting of the second gain block. g can be set to 1, 2, 4, 8. this sets the overall gain to 25, 50, 100, 200. the gain can then be fine tuned by using the calibration of the full scale point. 9. when calibrated. 10. v offset is the offset corrected by the offset calibration routine. v offset may be as large as 2t. cs5516, cs5520 ds74f1 5 ds74f2 5
dynamic characteristics parameter symbol ratio units ain and vref input sampling frequency f is f clk /128 hz modulator sampling frequency f s f clk /256 hz output update rate f out f clk /81,920 sps filter corner frequency f -3db f clk /341,334 hz settling time to 0.0007% (fs step) t s 6/f out s digital characteristics (t a = t min to t max ; va+, vd+ = 5v 5%; va-, vd- = -5v 5%; dgnd = 0) all measurements below are performed under static conditions. parameter symbol min typ max units high-level input voltage: xin all pins except xin v ih v ih 4.5 2.0 - - - - v v low-level input voltage xin all pins except xin v il v il - - - - 0.5 0.8 v v high-level output voltage (note 11) v oh (vd+)-1.0 - - v low-level output voltage l out = 1.6ma v ol --0.4v input leakage current l in -110 m a 3-state leakage current l oz -- 10 m a digital output pin capacitance c out -9-pf notes: 11. i out = -100 m a. this guarantees the ability to drive one ttl load. (v oh = 2.4v @ i out = -40 m a). cs5516, cs5520 6 ds74f1 6 ds74f2
recommended operating conditions (agnd, dgnd = 0v, see note 12.) parameter symbol min typ max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 5.5 -5.5 5.5 -5.5 v v v v differential analog reference voltage (vref+) - (vref-) 2.0 2.5 3.8 v analog input voltage: (note 13) unipolar bipolar vain vain 0 -t - - +t +t v v notes: 12. all voltages with respect to ground. 13. the cs5516 and cs5520 can accept input voltages up to +t in unipolar mode and -t to +t in bipolar mode where t=vref/(gx25). g is the gain setting at the second gain block. when the inputs exceed these values, the cs5516 and cs5520 will output positive full scale for any input above t, and negative full scale for inputs below agnd in unipolar and -t in bipolar mode. this applies when the analog input does not exceed 2t overrange. absolute maximum ratings* (agnd, dgnd = 0v, all voltages with respect to ground.) parameter symbol min typ max units dc power supplies: positive digital (note 14) negative digital positive analog negative analog vd+ vd- va+ va- -0.3 -0.3 -0.3 +0.3 - - - - (va+)+0.3 -5.5 5.5 -5.5 v v v v input current, any pin except supplies (notes 15, 16) l in -- 10 ma analog input voltage ain and vref pins v ina (va-)-0.3 - (va+)+0.3 v digital input voltage v ind -0.3 - (vd+)+0.3 v ambient operating temperature t a -55 - 125 c storage temperature t stg -65 - 150 c notes: 14. no pin should go more positive than (va+)+0.3v. vd+ must always be less than (va+)+0.3 v,and can never exceed 6.0v. 15. applies to all pins including continuous overvoltage conditions at the analog input pins. 16. transient currents of up to 100ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. * warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. cs5516, cs5520 ds74f1 7 ds74f2 7
msb msb-1 t 8 t 7 t 1 t 2 sod sclk cs lsb t 9 drdy msb msb-1 t 8 t 10 sod sclk lsb drdy t 14 t 15 t 12 t 13 msb-1 t 4 t 3 t 5 t 1 t 2 t 6 sid sclk t 1 t 2 t 9 msb sclk cs cs sid write timing (not to scale) sod read timing (not to scale) sod read timing with cs = 0 (not to scale) cs with continuous sclk (not to scale) cs5516, cs5520 8 ds74f1 8 ds74f2
switching characteristics (t a = t min to t max; va+, vd+ = 5v 5%; va-, vd- = -5v 5%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) parameter symbol min typ max units master clock frequency: internal oscillator / external clock xin 1.0 4.096 5.0 mhz master clock duty cycle 40 - 60 % rise times any digital input (note 18) any digital output t rise - - - 50 1.0 - m s ns fall times any digital input (note 18) any digital output t fall - - - 50 1.0 - m s ns startup power-on reset period t por - 100 - ms oscillator start-up time xtal = 4.9152 mhz(note 19) t ost -60-ms rst pulse width t res 1/xin - - ns serial port timing serial clock frequency sclk - - 2.4 mhz serial clock pulse width high pulse width low t 1 t 2 200 200 - - - - ns ns sid write timing cs enable to valid latch clock t 3 150 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 50 - - ns sclk falling prior to cs disable t 6 50 - - ns sod read timing cs to data valid t 7 - - 150 ns sclk falling to new data bit t 8 - - 170 ns sclk falling to sod hi-z t 9 - - 200 ns drdy falling to valid data (cs = 0) t 10 - - 150 ns cs rising to sod hi-z t 11 - - 150 ns cs disable hold time t 12 50 - - ns cs enable set-up time t 13 150 - - ns cs enable hold time t 14 50 - - ns cs disable set-up time t 15 150 - - ns notes: 18. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. 19. oscillator start-up time varies with crystal parameters. this specification does not apply when using an external clock source. cs5516, cs5520 ds74f1 9 ds74f2 9
general description the cs5516 and cs5520 are monolithic cmos a/d converters which include an instrumentation amplifier input, an on-chip programmable gain amplifier, and a dac for offset trimming. while the devices are optimized for ratiometric measurement of wheatstone bridge applications, they can be used for general purpose low-level signal measurement. each of the devices includes a two-channel dif- ferential delta-sigma modulator (the signal measurement input and the reference input are digitized independently before a digital output word is computed), a calibration microcontroller, a two-channel digital filter, a programmable in- strumentation amplifier block, a 4-bit dac for coarse offset trimming, circuitry for generation and demodulation of ac (actually switched dc) bridge excitation, and a serial port. the cs5516 outputs 16-bit words; the cs5520 outputs 20-bit words. the cs5516/20 devices can measure either unipolar or bipolar signals. self-calibration is utilized to maximize performance of the meas- urement system. to better understand the capabilities of the cs5516/20, it is helpful to ex- amine some of the error sources in bridge measurement systems. xout vd+ va+ vref+ vref- dgnd va- 1 m f ain+ ain- mdrv- 0.1 m f bx1 bx2 sclk sod sid smode cs5516 cs5520 xin 0.1 m f 10 w 0.1 m f vd- agnd2 mdrv+ drdy cs 10 w +5v analog supply -5v analog supply excitation supply synch. signals 0.1 m f 1 m f1 m f 1 m f 1 m f rst + - 1 2 12 11 9 10 6 7 5 8 agnd1 320 23 22 16 18 17 24 15 13 14 19 21 4 bridge excitation supply unused logic inputs must be connected to dgnd or vd+ optional clock source control logic serial data interface figure 1. system connection diagram: ac excitation mode using external excitation cs5516, cs5520 10 ds74f1 10 ds74f2
theory of operation the front page of this data sheet illustrates the block diagram of the cs5516 and cs5520 a/d converter. the device includes an instrumenta- tion amplifier with a fixed gain of 25. this chopper-stabilized instrumentation amplifier is followed by a programmable gain stage with gain settings of 1, 2, 4, and 8. the sensitivity of the input is a function of the programmable gain setting and of the reference voltage connected between the vref+ and vref- pins of the de- vice. the full scale of the converter is vref/( g x 25) in unipolar, or vref/(g x 25) in bipolar, where vref is the reference voltage between the vref+ and vref- pins, g is the gain set- ting of the programmable gain amplifier, and 25 is the gain of the instrumentation amplifier. after the programmable gain block, the output of a 4-bit dac is combined with the input sig- nal. the dac can be used to add or subtract offset from the analog input signal. offsets as large as 200 % of full scale can be trimmed from the input signal. the cs5516 and cs5520 are optimized to per- form ratiometric measurement of bridge-type transducers. the devices support dc bridge exci- tation or two modes of ac (switched dc) bridge excitation. in the switched-dc modes of opera- tion the converter fully demodulates both the reference voltage and the analog input signal from the bridge. xout vd+ va+ vref+ vref- dgnd va- 1 m f ain+ ain- mdrv- 0.1 m f sclk sod sid smode cs5516 cs5520 xin 0.1 m f 10 w 0.1 m f vd- agnd2 mdrv+ drdy cs 10 w +5v analog supply -5v analog supply 0.1 m f 1 m f1 m f 1 m f 1 m f rst + - 1 2 9 10 6 7 5 8 agnd1 320 23 22 16 18 17 24 15 13 14 19 21 4 unused logic inputs must be connected to dgnd or vd+ optional clock source control logic serial data interface figure 2. system connection diagram: dc excitation mode (exc bit = 0), f1 = f0 = 0. cs5516, cs5520 ds74f1 11 ds74f2 11
the cs5516/20 includes a microcontroller which manages operation of the chip. included in the microcontroller are eight different registers asso- ciated with the operation of the device. an 8-bit command register is used to interpret instruc- tions received via the serial port. when power is applied, and the device has been reset, the se- rial port is initialized into the command mode. in this mode it is waiting to receive an 8-bit command via its serial port. the first 8 bits into the serial port are placed into the command reg- ister. table 1 lists all the valid command words for reading from or writing to internal registers of the converter. once a valid 8-bit command word has been received and decoded, the serial port goes into data mode. in data mode the next 24 serial clock pulses shift data either into or out of the serial port. when writing data to the port, the data may immediately follow the command word. when reading data from the port, the user must pause after clocking in the 8-bit command word to allow the microcontroller time to decode the command word, access the appropriate regis- ter to be read, and present its 24-bit word to the port. the microcontroller will signal when the 24-bit read data is available by causing the drdy pin to go low. the user must write or read the full 24-bit word except in the case of reading conversion data. in read data conversion mode, the user may read less than 24 bits if cs is then made inactive ( cs = 1). cs going inactive releases user control over the port and allows new data updates to the port. the user can instruct the on-chip microcontroller to perform certain operations via the configura- tion register. whenever a new word is written to the 24-bit configuration register, the micro- controller then decodes the word and executes the configuration register instructions. table 2 illustrates the bits of the configuration register. the bits in the configuration register will be dis- cussed in various sections of this data sheet. command register d7 d6 d5 d4 d3 d2 d1 d0 1 rsb2 rsb1 rsb0 r/ w0 0 0 bit name value function d7 d7 1 must always be logic 1 rsb2-0 register select bit 000 001 010 011 100 101 110 111 selects register to be read or written per r/ w bit conversion data (read only) configuration gain dac ratiometric offset non-ratiometric offset - ain non-ratiometric offset - vref not used r/ w read/ write 0 1 write to the register selected by the rsb2-0 bits read from the register selected by the rsb2-0 bits d2 d1 d0 d2 d1 d0 0 0 0 not used not used not used table 1. cs5516 and cs5520 commands cs5516, cs5520 12 ds74f1 12 ds74f2
configuration register d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 register dac3 dac2 dac1 dac0 exc f1 f0 d16 g1 g0 u/b d12 reset (r) 000000000000 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register a/s ec d9 d8 cc3 cc2 cc1 cc0 d3 d2 d1 rf reset (r) 000000000000 bit name value function dac3 dac sign bit 0 1 r 1 add offset subtract offset this bit is read only 2 dac2-0 dac bits 000 001 010 011 100 101 110 111 r 25% offset 50% offset 75% offset 100% offset these bits are read only 2 125% offset 150% offset 175% offset exc excitation: internal external 0 1 r bx1 and bx2 outputs are determined by bits f1 and f0 bx1 is an input which determines the phase of the demodulation clock and the bx2 output f1-f0 select frequency 00 01 10 11 r excitation on bx1 & bx2 is dc. bx1=0 v, bx2=+5 v excitation frequency on bx1 & bx2 is xin/8192 hz excitation frequency on bx1 & bx2 is xin/16384 hz excitation frequency on bx1 & bx2 is xin/4096 hz d16 d16 0 r must always be logic 0 g1-g0 select pga gain 00 10 01 11 r gain = 1 (x25) gain = 2 (x25) gain = 4 (x25) gain = 8 (x25) u/b select unipolar/bipo- lar mode 0 1 r bipolar measurement mode unipolar measurement mode d12 d12 0 r must always be logic 0 a/s awake/sleep 0 1 r awake mode sleep mode ec execute calibration 0 1 r calibration not active perform calibration selected by cc3-cc0 bits. ec bit must be written back to "0" after calibration is completed d9 d9 0 r must always be logic 0 d8 d8 0 r must always be logic 0 cc3-cc0 calibration control bits 0000 1000 0100 0010 0001 r no calibration to be performed calibrate non-ratiometric offset, vref calibrate non-ratiometric offset, ain calibrate ratiometric offset, ain calibrate gain, ain d3 d3 0 r must always be logic 0 d2 d2 0 r must always be logic 0 d1 d2 0 r must always be logic 0 rf reset filter 0 1 r normal operation reset filter notes: 1.reset state 2.a write to these bits does not change the register bit values. these bits are just a mirror of the dac register contents. table 2. configuration register cs5516, cs5520 ds74f1 13 ds74f2 13
system initialization whenever power is applied to the cs5516/cs5520 a/d converters, the devices must be reset to a known condition before proper operation can occur. the internal reset is applied after power is established and lasts for approximately 100 ms. the rst pin can also be used to establish a reset condition. the reset sig- nal should remain low for at least one xin clock cycle to ensure adequate reset time. it is recom- mended that the rst pin be used to reset the converter if the power supplies rise very slowly or with poor startup characteristics. the rst signal can be generated by a microcontroller out- put, or by use of an r-c circuit. the reset function initializes the configuration register and all five of the calibration registers; and places the microcontroller in command mode ready to accept a command from the serial port. whenever the device is reset the drdy pin will be set to a logic 1 and the on-chip regis- ters are initialized to the following states: configuration 000000(h) calibration registers: dac 000000(h) gain 800000(h) ain ratiometric offset 000000(h) ain non-ratiometric offset 000000(h) vref non-ratiometric offset 000000(h) calibration after the cs5516/20 is reset, the device is func- tional and can perform measurements without being calibrated. the converter will utilize the initialized values of the calibration registers to calculate output words. the converter uses the two outputs (ain & vref) of the dual channel converter along with the contents of the calibration registers to com- pute the conversion data word. the following equation indicates the computation. r0 = r4 [ [ d ain - r1 d vref - r2 ] - r3 ] where r0 is the output data, d ain and d vref are the digital output words from the ain and vref digital filter channels, and r1, r2, r3 and r4 are the contents of the following calibra- tion registers: r1 = ain non-ratiometric offset r2 = vref non-ratiometric offset r3 = ain ratiometric offset r4 = gain the computed output word, r0, is a twos com- plement number. calibration minimizes the errors in the converted output data. if calibration has not been per- formed, the measurements will include offset and gain errors of the entire system. the converter may be calibrated each time it is powered up, or calibration words from a pre- vious calibration may be uploaded into the appropriate calibration registers from some type of e 2 prom by the system microcontroller. the converter uses five different registers to store specific calibration information. each of the calibration registers stores information perti- nent to correcting a specific source of error associated with either the converter or with the input transducer and its wiring. the method by cs5516, cs5520 14 ds74f1 14 ds74f2
which calibration is initiated is common to each of the calibration registers. the configuration register controls the execution of the calibration process. bits cc3--cc0 in the configuration register determine which type of calibration will be performed and which of the five calibration registers will be affected. on the falling edge of the 24th sclk, the configuration word will be latched into the configuration register and the se- lected calibration will be executed. the time required to perform a calibration is listed in ta- ble 3. the drdy pin will remain a logic 1 during calibration, and will go low when the calibration step is completed. the serial port should not be accessed while a calibration is in progress. the ec bit of the configuration register remains a logic 1 until it is overwritten by a new configuration word (ec = 0). consequently, if ec is left active, any write (the falling edge of the 24th sclk) to any regis- ter inside the converter will cause a re-execution of the calibration sequence. this occurs because the internal microcontroller executes the contents of the configuration register every time the 24th sclk falls after writing a 24-bit word to any internal register. to be certain that calibrations will not be re-executed each time a new word is written or read via the serial port, the ec bit of the configuration register must be written back to a logic 0 after the final calibration step has been completed. the cc3--cc0 bits of the configuration register determine the type of calibration to be per- formed. the calibration steps should be per- formed in the following sequence. if the user determines that non-ratiometric offset calibra- tion is important, the non-ratiometric offset errors of the vref and ain input channels should be calibrated first. then the ratiometric offset of the ain channel should be calibrated. and finally, the ain channel gain should be calibrated. non-ratiometric errors to calibrate out the vref and ain non-ratiometric errors, the input channels to the vref path into the converter and the ain path into the converter must be grounded (this may occur at the pins of the ic, or at the bridge exci- tation as shown in figure 3.). then the ec, cc2 and cc3 bits of the configuration register must be set to logic 1. the converter will then perform a non-ratiometric calibration and place configuration register cal type calibration time ec cc3 cc2 cc1 cc0 11000 vref non-ratiometric offset 573,440/fclk 10100 ain non-ratiometric offset 573,440/fclk 10010 ain ratiometric offset 2,211,840/fclk 10001 ain system gain 573,440/fclk 11100vref & ain non-ratiometric offset 573,440/fclk 0xxxx end calibration - drdy remains high through calibration sequence. in all modes, drdy falls immediately upon completion of the calibration sequence. table 3. cs5516/cs5520 calibration control vref+ vref- ain+ ain- bx1 bx2 1a* 1b* cs5516 cs5520 *note: the bridge can be grounded with a relay or with jumpers to perform non-ratiometric calibration. - + figure 3. non-ratiometric system calibration using internal excitation cs5516, cs5520 ds74f1 15 ds74f2 15
the proper 24 bit calibration words in the vref and ain non-ratiometric registers. note that the two non-ratiometric offsets can be calibrated si- multaneously or independently, but they must be calibrated prior to the other calibration steps if non-ratiometric offset calibration is to be used. if the effects of the non-ratiometric errors are not significant enough to affect the user application, they can be left uncalibrated (after a reset, the non-ratiometric offset registers will contain 000000(h)). ratiometric offset once the non-ratiometric errors have been cali- brated, the ratiometric offset error of the ain channel should be calibrated next. to perform this calibration step, a reference voltage must be applied to the vref+ and vref- pins. then, place "zero" weight on the scale platform. this will result in an offset voltage into the converter which will represent the offset of the bridge, the wiring, and the ain input of the converter itself. a configuration word with the ec and cc1 bits set to logic 1 is then written into the configura- tion register. during the ratiometric offset calibration of ain the microcontroller first uses a successive approximation algorithm to com- pute the correct values for the dac3-dac0 bits of the dac register. this accommodates any large offsets on the ain input signal. once the four dac bits are computed, this amount of off- set is removed from the input signal. the microcontroller then computes the appropriate 24 bit number to place in the ain ratiometric offset register to calibrate out the remaining off- set not removed by the dac. gain after the ain ratiometric offset has been cali- brated, the next step is to perform a gain calibration. gain calibration is performed with "full scale" weight on the scale platform. the ec and cc0 bits of the configuration register are set to logic 1. the gain calibration of the ain channel is the final calibration step. after drdy falls to signal the completion of this cali- bration step, the ec bit of the configuration register must be set back to logic 0 to terminate the calibration mode. limitations in calibration range there are five calibration registers in the con- verter. there are two non-ratiometric offset calibration registers, one for the ain input and one for the vref input; one 4-bit offset trim dac; one ratiometric offset calibration register for the ain input; and one gain calibration reg- ister. after the non-ratiometric offsets are calibrated, an lsb in either of the 24-bit non-ra- tiometric calibration registers represents 2 -23 proportion of an internally-scaled mdrv (modulator differential reference voltage). at the mdrv+ and mdrv- pins, the mdrv has a nominal value of 3.75 volts. this voltage is in- ternally scaled to a nominal 2.5 volts (never less than 2.4 volts) for use with the non-ratiometric calibration. the two non-ratiometric calibration words are stored in 2s complement form with one count equal to slightly less than 300 nv at the input of the internal a/d converter. for the ain channel this will be scaled down by the gain of the instrumentation amplifier (x25) and the pga gain. for a pga gain = 1, one count of a non-ratiometric register will represent slightly less than 12 nv. non-ratiometric offset at the vref input cannot exceed 2.4 volts to be within calibration range of the converter. non- ratiometric offset to be calibrated by the ain channel cannot exceed 2.4 volts divided by the channel gain. with a pga gain = 1, the maxi- mum non-ratiometric offset which can be calibrated on the ain channel cannot exceed 96 mv. when the ratiometric offset is calibrated, the 4- bit dac coarsely trims offset from the analog signal. the ratiometric offset which remains is finely trimmed after the signal has been con- verted; using the contents of the ratiometric offset register for digital correction. the dac cs5516, cs5520 16 ds74f1 16 ds74f2
bits can be manipulated by the user to add or subtract offset up to 200 percent of the nominal input signal. the ain ratiometric offset register can be manipulated to add or subtract offset equal to the maximum differential input signal into the x25 amplifier. an lsb in the ratiomet- ric offset register represents 2 -23 proportion of the voltage input across the vref+ and vref- pins at the internal input to the ain channel a/d converter. this will be scaled down by the ain channel gain when calculated relative to the instrumentation amplifier input. for example, with a vref = 2.5 v, the pga gain = 1, one count of the ratiometric offset register would represent about 12 nv at the instrumentation am- plifier input. the proportion remains ratiometric even if the vref voltage should change. the 24-bit register content is stored in 2s comple- ment form. manipulation of the dac or ratiometric offset register allows the user to shift the transfer func- tion to allow for load cell creep or load cell zero drift. the gain calibration is performed last. the con- tents of the gain register spans from 2 -23 to 2 as shown in table 4. after gain calibration has been performed, the numeric value in the gain register should not exceed the range of 0.8 to 1.2. the gain calibration range is 20 % of the nominal value of 1.0. the nominal value of 1.0 is for an input span dictated by the vref volt- age, the pga gain, and the x25 instrumentation gain. the converter may operate with gain slope factors from 0.5 to 2.0 (decimal), but when the slope exceeds 1.2 the converter output code computation may lack adequate resolution and result in missing codes in the transfer function. internal circuitry may saturate for large signals which would calibrate to a gain factor less than 0.8. in a typical weigh scale application, the cs5516/cs5520 will be calibrated in combina- tion with a load cell at the factory. once calibrated, the calibration words are off-loaded from the converter and stored in e 2 prom. when powered-up in the field the calibration words are up-loaded into the appropriate regis- ters. this is viable because the ain and vref input to the converter are "chopper-stabilized" and maintain excellent stability when subjected to changes in temperature. programmable gain amplifier the programmable gain amplifier inside the cs5516/20 offers gains of 1, 2, 4, and 8. this is in addition to the fixed gain of 25 in the input instrumentation amplifier. the gain tracking of the pga is about one percent between ranges. the user can remove this error by performing a gain calibration at the factory with a full scale signal on each range. the gain calibration word for each gain range can be off-loaded into e 2 prom and uploaded into the gain register whenever a new gain setting is selected for the pga. gain stability over temperature for the converter itself is approximately 1 ppm/ c when the device is used ratiometrically. serial interface modes the cs5516/20 support either 5, 4 or 3 pin se- rial interfacing. the smode pin sets the operating mode of the serial interface. with smode = 0, the device assumes the user is op- erating with either a 5 or 4 wire interface. the five wire mode includes sod, sid, sclk, drdy, and cs. in the four wire mode, cs is connected to dgnd as a logic 0. the user would then interface to the sod, sid, sclk, and drdy pins. cs5516, cs5520 ds74f1 17 ds74f2 17
ain and vref non-ratiometric offset registers msb lsb register 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 reset (r) 000000 000000 ? one lsb represents 2 -23 proportion of the internal mdrv ( ? 2.5 volts) dac register d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 register dac3 dac2 dac1 dac0 exc f1 f0 d16 g1 g0 u/b d12 reset (r) 000000000000 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register a/s ec d9 d8 cc3 cc2 cc1 cc0 d3 d2 d1 rf reset (r) 000000000000 bit name value function dac3 dac sign bit 0 1 r 1 add offset subtract offset dac2-0 dac bits 000 001 010 011 100 101 110 111 r 25% offset 50% offset 75% offset 100% offset 125% offset 150% offset 175% offset bits d19 to d0 0 r these bits mirror the read only 2 configuration register note: 1. reset state 2. a write to these bits does not change the register bit values. ain ratiometric offset register msb lsb register 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 reset (r) 000000 000000 ? one lsb represents 2 -23 proportion of the voltage [<(vref+) - (vref-)>/gain] where gain = 25 x pga gain gain register msb lsb register 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 reset (r) 100000 000000 ? the gain register span from 0 to (2-2 -23 ). after reset the msb=1, all other bits are 0. table 4. calibration registers cs5516, cs5520 18 ds74f1 18 ds74f2
reading a register in the converter requires a command word to be written to the sid pin. for example, to read the conversion data regis- ter, the following command sequence should be performed. first, the command word 88(h) would be issued to the port. in the 5 wire inter- face mode, this would involve activating cs low, followed by 8 sclks (note that sclk must always start low and transition from low to high to latch the transmit data, and then back low again) to input the 8-bit command word. cs must be low for the serial port to recognize sclks during a write or a read, but it is actually the first rising sclk during command time that gives the user control over the port. after writ- ing the command word, the user must pause and wait until the cs5520 presents the selected reg- ister data to the serial port. the drdy signal will fall when the data is available. when read- ing the conversion data register, it may take up to 112,000 xin clock cycles for drdy to fall after the 88(h) command word is recognized. see figure 4 for an illustration of command and data word timing. the conversion data register is actually the accu- mulator of the post-processor which computes the output data. at the end of each filter convo- lution cycle, the internal microcontroller checks to see if a read conversion data register com- mand has been interpreted. if so, it transfers the accumulator result to the serial port. whenever registers other than the conversion data register are read, the drdy pin will fall within 256 xin clock cycles (62.5 m s with xin = 4.096 mhz) after the command word is recognized. when drdy falls, 24 sclks are then issued to the port to read the 24-bit output data word. drdy will return high after all 24 bits have been clocked out. the sod pin will be in a hi-z state whenever cs is high, or after all 24 output data bits have been clocked out of the port. the cs5516/20 is designed such that it can out- put conversion data words continuously, without issuing a new command word prior to each data read. under the following circumstances, con- tinuous conversion data can be read from the port after issuing only one 88(h) command word. once the command to read the conversion data register is issued, drdy must be allowed to go low, after which 24 sclks are issued to read the data. this will cause drdy to return high. the converter will continue to output conversion words at the update rate as long as a different command word is not started prior to drdy falling again. the user is not required to read every output word to remain in the continuous update mode. drdy will toggle high, and then low as each new output word becomes available. if a command word is issued immediately after a data word is read, the converter will end the read conversion mode. figure 5 illustrates the con- tinuous data mode. the user should perform all data reads and com- mand writes within 51,000 xin clock cycles after drdy falls to avoid ambiguity as to who controls the serial port. if smode = 1 (tied to vd+), the interface oper- ates as a 3 wire interface using only sod, sid, and sclk. in the 3 wire mode cs must be tied to dgnd. drdy operates normally but is not used. instead, the drdy signal modifies the behavior of the sod signal, allowing it to signal to the user when data is available. to read data from the converter requires a command word to be written to the sid pin. the sod output is normally high (never hi-z). when output data is available, the sod signal will go low. the user would then issue 8 sclks to the sclk pin to clear this data ready signal. on the falling edge of the 8th sclk the sod pin will present the first bit of the 24-bit output word. 24 sclks are then issued to read the data. then sod will go high. sid should remain low whenever the cs5516, cs5520 ds74f1 19 ds74f2 19
command time 8 sclks data time 24 sclks command time 8 sclks data time 24 sclks sid write sod read (4 or 5 wire) t * d cs sclk sid cs sclk sid drdy sod command time 8 sclks 8 sclks clear drdy sod read (3 wire) sod sclk sid t * d data time 24 sclks msb lsb sod falls if command was 88(h) msb lsb msb lsb 81,920 xin clock cycles figure 4. command and data word timing *see text for t d time. cs5516, cs5520 20 ds74f1 20 ds74f2
sid pin is not being written. when reading sod, sclk cannot be continuous but must burst one clock cycle per bit. the continuous read conversion data mode is also functional in the 3-wire interface mode. is- sue one 88(h) command word to the converter. then wait for sod to go low. issue 8 sclks to clear the data ready function. the msb data bit will then appear on the sod pin. issue 24 sclks to read the conversion word. at the fall- ing edge of the 24th sclk sod will return high. sod will go low at the next drdy falling time to indicate a new conversion word. eight sclks must again be issued to clear the data ready function before clocking out the data con- version word. the sod pin will continue to toggle low each time a word is available even if the conversion data is not read. to terminate the continuous conversion mode, input an 8-bit com- mand word immediately after reading a conversion word. the user should perform all data reads and com- mand writes within 51,000 xin clock cycles after sod falls to avoid ambiguity as to who controls the serial port. serial port initialization if for any reason the off-chip microcontroller fails to know whether the serial port of the cs5516/20 is in data mode or command mode, the following initialization procedure can be is- sued to the port to force the cs5516/20 into the command mode. write 128 or more 1s to the sid pin. then issue a single 0 to the sid pin. the port will then be initialized into the com- mand mode and will be waiting for an 8-bit command word. bridge excitation options the cs5516/cs5520 a/d converters are opti- mized for wheatstone bridge applications. the converters support either dc or ac (switched dc) bridge excitation. dc bridge excitation the cs5516/cs5520 can be configured for dc bridge excitation in either of two ways. the exc bit of the configuration register can be set for either internal or for external excitation. if set to internally-controlled mode (exc = 0), the f1 and f0 bits must be set to logic 0s. in this condition, the bridge can be excited from a dc supply with a resistor divider to develop the ap- propriate reference voltage for the vref+ and vref- pins. note that the bridge excitation 8 data bits 24 data bits cs sclk sid drdy sod 24 data bits 8 sclks 24 sclks 24 sclks port access period valid 51,000 xin clock cycles 81,920 xin clock cycles figure 5. continuous read conversion data mode (4 or 5 wire) cs5516, cs5520 ds74f1 21 ds74f2 21
should not be applied prior to the cs5516/cs5520 being powered-up. with exc, f1, and f0 set to logic 0, the bx1 output will be logic 0 (0 volts) and the bx2 output will be a logic 1 (+5 volts). a second method for configuring the converter for dc excitation is by setting exc = 1, and pulling up bx1 (pin 12) to vd+ (pin 20) through a resistor. this sets the converter for use with external excitation which uses the bx1 pin as an input to set the excitation fre- quency. with bx1 = vd+, the external excitation frequency is zero, or dc. ac bridge excitation ac bridge excitation involves using a clock sig- nal to generate a square wave which repetitively reverses the excitation polarity on the bridge. to excite the bridge dynamically requires some type of bridge driver external to the cs5516/cs5520 converter. this driver is driven by a square wave clock. the source of this clock depends upon whether the converter is set for internal excita- tion or for external excitation. figure 6 illustrates a sample bridge drive circuit when op- erating in the internal ac excitation mode. using internal excitation involves setting the exc bit of the configuration register to 0, and setting the f1 and f0 bits to select the excitation frequency for the bridge. in this mode the exci- tation frequency is a sub-multiple of the xin clock frequency. the excitation clock is output from the bx1 and bx2 pins of the converter in the form of a two-phase non-overlapping clock. the converter is capable of demodulating this clocked excitation. but only if the signals into the ain+ and vref+ pins of the converter are in phase with the demodulation clock inside the converter (see figure 7). the non-overlapping clock signals from bx1 and bx2 are cmos level outputs (0 to vd+ volts) and are capable of driving one ttl load. a buffer amplifier must be used to drive the bridge. whenever the internal mode is used for dynamic bridge excitation the signals are non-overlap- ping. the non-overlapping time is one xin clock cycle. the converter can also be configured to provide dynamic bridge excitation when operating in the external-controlled bridge excitation mode. with the exc bit of the configuration register set to logic 1, the bx1 pin becomes an input which determines the bridge excitation frequency and phase. bx1 should be near 50% duty cycle. the user can select the excitation frequency with the following restrictions. the excitation frequency must be synchronous with the xin frequency of the converter and must be chosen using the fol- lowing equation: f exc = ( n xin ) 81,920 where n is an integer and lies in the range in- cluding 1 to 160. f exc is the desired bridge excitation frequency. other asynchronous fre- 2 4 3 5 7 6 10 m f 0.1 m f + -5v +5v 100 k -5v 10 k 10 k micrel mic4428 or mic4425 bx2 +5v 0v tp0610 exc+ exc- +5v -5v +5v -5v figure 6. sample ac bridge driver bx1 (out) bx2 (out) demod clock (internal) note: the signals from the bridge into ain+ and vref+ of the converter must be in phase with the demodulation clock. t is 1 cycle of xin clock. d t d t d figure 7. internal excitation clock phasing cs5516, cs5520 22 ds74f1 22 ds74f2
quencies are possible but may introduce a jitter component in the bx output signals. it is de- sirable not to choose an excitation frequency where interference components are present, such as 50 hz or 60 hz or their harmonics. the xin frequency can be divided down using a counter ic external to the a/d converter. f exc would be input to the bx1 pin of the converter to synchronize the internal operations of the am- plifiers and synchronous detection circuitry and to generate a clock output from the bx2 pin. the bx2 output is then used to drive the bridge amplifier with a signal of proper phase for detec- tion by the converter. figure 8 indicates the necessary phase of the signals to ensure proper demodulation. whenever the dynamic excitation clock output from either the bx1 and bx2 pins (during inter- nal excitation) or from the bx2 pin (during external excitation) changes states, the converter waits 64 xin cycles before sampling the ain and vref signal inputs. the delay allows some time for the signal to settle from the modulation event. input filtering some load cells are located a distance from the input to the converter. under these conditions, separate twisted pair cabling is recommended for the excitation drive to the bridge, the excitation sense leads (if used), and for the ain /ain- signal leads. if the ain+/ain- leads to the con- verter and the vref+/vref- leads to the con- verter are filtered, care should be exercised in the choice of components. with either dc or ac excitation, one should limit any input filtering resistors on ain to below 1 k w . values greater than this will degrade noise performance of the converter. in ac excitation applications, any fil- tering must be broadband enough that the switched dc excitation signal can settle within 10 m secs. failure to meet this settling requirement will affect measurement accuracy. figure 9 illus- trates acceptable filter components for ac excitation. if only differential filtering is re- quired, a single capacitor can be placed between ain+ and ain- (and vref+ and vref-) in place of two capacitors to ground. voltage reference considerations the cs5516/20 include an on-chip voltage refer- ence which is output on the mdrv- and referenced from the mdrv+ pin. the converter is designed to be operated as a ratiometric meas- urement device. the 2-channel delta-sigma converter uses the internal mdvr (modulator differential voltage reference) as its reference. since the mdvr is used for converting both the ain and vref signals at the same time, the ab- solute value of the mdvr and its tempco are not important when the cs5516/20 is used in the ratiometric measurement mode. the voltage ref- erence output, mdvr-, should be decoupled using a 1 m f capacitor which is connected to the mdrv+ supply line. voltage reference decou- bx1 (in) bx2 (out) demod clock (internal) t dd note: the signals from the bridge into ain+ and vref+ of the converter must be in phase with the demodulation clock. t 64/xin dd figure 8. external excitation clock phasing cs5516 or cs5520 vref+ vref- ain+ ain- 470 pf 470 pf 7.5k 7.5k 5k exc+ exc- 0.0047 m f 0.0047 m f 300 300 ain+ ain- figure 9. ain and vref input filter components cs5516, cs5520 ds74f1 23 ds74f2 23
pling is shown on the system connection dia- grams. if absolute measurements are to be made by the cs5516/20, then a precision reference should be input into the vref+ and vref- terminals. clock generator the cs5516/20 includes a gate which can be connected as a crystal oscillator to provide the master clock to run the chip. alternatively, an external (cmos compatible) clock can be input into the xin pin. figure 10 illustrates a simple model for the on-chip gate oscillator. the on- chip oscillator is designed to typically operate with crystal frequencies between 4.0 and 5.0 mhz without additional loading capacitors. if other crystal frequencies, or if ceramic resona- tors are used, additional loading capacitance may be necessary. the xout pin can be used to drive one cmos gate for system clock requirements. be sure to include the gates input capacitance and stray ca- pacitance as part of the loading capacitance for the resonating element. digital filter the cs5516/20 is optimized to operate with clock frequencies of 4.096 mhz or 4.9152 mhz. these result in the filter having a 3db bandwidth of 12 hz or 15 hz, with output word rates of 50 or 60 sps . the rejection at 50hz 3hz is 70 db mini- mum with a 4.096 mhz clock. similar rejection is obtained at 60 hz with a 4.9152 mhz clock. the digital filter has a deep notch in its transfer function at 50 hz (xin = 4.096 mhz) or 60 hz (xin = 4.9152 mhz) but other xin frequencies can be used. the filter transfer function will scale proportionally. figure 11 shows the trans- fer function of the filter when operated at three different frequencies. with a 3.579 mhz xin, the filter offers greater than 90 db rejection of both 50 and 60 hz. the output word rate of the converter scales with the xin clock rate and is set by the ratio of xin/81,920; or 50 sps for xin = 4.096 mhz. if very narrow signal bandwidths, such as 3 hz, are desired, averaging of the output words is rec- ommended. >1m to internal circuitry 400 xout 5pf 1pf 23 22 400 external xtal 1pf 5pf xin m g @ 2000 umhos figure 10. on-chip gate oscillator model input frequency (hz) -160 -140 -120 -100 -80 -60 -40 -20 0 magnitude (db) (1) xin = 3.579 mhz (2) xin = 4.096 mhz (3) xin = 4.915 mhz 0 0 0 21.8 25 30 43.7 50 60 87.3 100 120 131.0 150 180 174.7 200 240 218.5 250 300 figure 11. filter magnitude response 0 5 10 15 20 25 30 35 40 45 50 input frequency (hz) -180 -150 -120 -90 -60 -30 0 30 60 90 120 150 180 phase (degrees) xin = 4.096 mhz figure 12. filter phase response. cs5516, cs5520 24 ds74f1 24 ds74f2
the digital filter computes a new output data word every 81,920 xin clock cycles. if the in- put experiences a large change in amplitude, the pga gain is changed, or the dac calibration registers are changed, it may take up to six filter cycles (81,920 x 6 clock cycles) for the filter to compute an output word which is fully settled to the input signal. output coding the cs5516/20 converters output data in binary format when operating in unipolar mode and in twos complement when operating in bipolar mode. table 5 illustrates the output coding for the converters. note that when reading conver- sion data from the converter the data word is output msb or sign bit first. falling edges on sclk advance the data word to the next lower bit. the output conversion words from both the cs5516 and the cs5520 are 24 bits long. the cs5516 has 16 data bits followed by 8 flag bits (all identical). the cs5520 has 20 data bits fol- lowed by 4 flag bits (all identical). to read the conversion data, including the error flag infor- mation will require at least 17 sclks for the cs5516 and at least 21 sclks for the cs5520. under normal operating conditions, the flag bits will be zeroes. the flag bits will be set to all ones whenever an overrange condition exists. under large overrange conditions where the in- put signal exceeds the nominal full scale input by approximately two times (for example: 50 mv input when the nominal full scale input is set-up for 25 mv), the converter may be un- able to compute a proper output code. in this condition flag bits will be set to all 1s but the conversion data may be a value other than full scale plus or minus. after the converter is first powered-up, a rst is issued, or the device comes out of the sleep mode, the first conversion data read may erroneously have its error flag bits set to "1". synchronizing multiple converters multiple converters can be made to output their conversion words at the same time if they are operated from the same clock signal at xin. to synchronize multiple converters requires that they all have their rf bit of the configuration register written to a logic 1 and then back to 0. the filters will be allowed to start convolutions after the falling edge of the 24th sclk used to write the rf bit to the configuration register. unipolar input voltage offset binary bipolar input voltage twos complement unipolar input voltage offset binary bipolar input voltage twos complement >(vfs-1.5 lsb) ffff >(vfs-1.5 lsb) 7fff >(vfs-1.5 lsb) fffff >(vfs-1.5 lsb) 7ffff vfs-1.5 lsb ffff ----- ffff vfs-1.5 lsb 7fff ----- 7ffe vfs-1.5 lsb fffff ----- ffffe vfs-1.5 lsb 7ffff ----- 7fffe vfs/2-0.5 lsb 8000 ----- 7fff -0.5 lsb 0000 ----- ffff vfs/2-0.5 lsb 80000 ----- 7ffff -0.5 lsb 00000 ----- fffff +0.5 lsb 0001 ----- 0000 -vfs+0.5 lsb 8001 ----- 8000 +0.5 lsb 00001 ----- 00000 -vfs+0.5 lsb 80001 ----- 80000 <(+0.5 lsb) 0000 <(-vfs+0.5 lsb) 8000 <(+0.5 lsb) 00000 <(-vfs+0.5 lsb) 80000 cs5516 output coding cs5520 output coding note: vfs in the table equals the full scale voltage between +vref/(g x 25) and ground for unipolar mode; and between vref/(g x 25) for bipolar mode. the signal input to the a/d section of the converter has been amplified by the instrumentation amplifier (x25) and the pga gain, g (1, 2, 4, or 8). see text about error flags under overrange conditions. table 5. output coding for the cs5516/20 converters. cs5516, cs5520 ds74f1 25 ds74f2 25
the filter will start a new convolution on the next rising edge of the xin clock after the 24th sclk falls. sleep mode the cs5516/20 configuration register has an a/s bit which allows the users to put the device in a sleep condition to lower quiescent power. upon reset the a/s bit device is set to a logic 0 which places the device in the awake condi- tion. writing a 1 to the a/s bit will shutdown most of the chip, including the oscillator. it is desirable to use the following sequence when coming out of sleep. write a logic 0 to the a/s bit of the configuration register. in the same configuration word write a logic 1 to the rf bit of the configuration register. then wait until it is certain that the oscillator has started. after the oscillator has started or a clock present on the xin pin, set the rf bit back to 0. the user should then wait at least 6 output word update periods before expecting a valid output data word. noise performance typical noise performance for the converter is listed in the specification tables for each pga gain. figure 13 illustrates a noise histogram for 1000 output conversions from the cs5520. the data for the histogram was collected using the cdb5520 evaluation board; with vref at 2.5 volts, pga = 4, bipolar mode. the data shows the standard deviation of the data set is 3.2 lsbs. one lsb is equivalent to [vref x 2(bi- polar)]/ [inst amp gain x pga gain x number of codes] or (2.5 x 2)/ (25 x 4 x 2e20) = 47.7 nv. one standard deviation is equivalent to rms if the data is normal or gaussian. the rms noise presented by the plot is 153 nv, which is in good agreement with the typical noise specifica- tion of 150 nv for a pga gain of 4. applications see the application notes section of the databook. schematic & layout review service confirm optimum schematic & layout before building your board. confirm optimum schematic & layout before building your board. for our free review service call applications engineering. for our free review service call applications engineering. call: (512) 445-7222 0 20 40 60 80 100 120 140 012345678 -1 -2 -3 -4 -5 -6 -7 -8 figure 13. cs5520 noise histogram. cs5516, cs5520 26 ds74f1 26 ds74f2
pin descriptions power supply connections vd+ - positive digital power, pin 20. positive digital supply voltage. nominally +5 volts. vd- - negative digital power, pin 21. negative digital supply voltage. nominally -5 volts. dgnd - digital ground, pin 19. digital ground. va+ - positive analog power, pin 3. positive analog supply voltage. nominally +5 volts. va- - negative analog power, pin 4. negative analog supply voltage. nominally -5 volts. agnd1, agnd2 - analog ground, pins 5, 8. analog ground. clock generator xin; xout - crystal in; crystal out, pins 22, 23 an internal gate is connected to these pins enabling the use of either a crystal or a ceramic resonator to provide the master clock for the device. alternatively, an external (cmos compatible) clock can be input to the xin pin as the master clock for the device. 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 10 11 12 15 14 13 modulator diff. voltage ref + mdrv+ smode serial interface mode modulator diff. voltage ref - mdrv- xout crystal out positive analog power va+ xin crystal in negative analog power va- vd- negative digital power analog ground one agnd1 vd+ positive digital power analog in + ain+ dgnd digital ground analog in - ain- sod serial output data analog ground two agnd2 sid serial input data voltage ref in + vref+ sclk serial clock input voltage ref in - vref- drdy data ready bridge excite 2 bx2 cs chip select bridge excite 1 bx1 rst reset cs5516, cs5520 ds74f1 27 ds74f2 27
digital inputs rst - reset, pin 13. reset pin initializes all calibration registers to a known condition and places the serial port into the command mode. cs - chip select, pin 14. an input which can be enabled by an external device to gain control over the serial port. when this pin is high, sod is in a high impedance state if smode = 0. sclk - serial data clock, pin 16. a clock signal at this pin determines the output rate of the data from the sod pin and the input data rate on the sid pin. sid - serial input data, pin 17. this pin is used for inputting command and configuration words or inputting calibration words. data is input at a rate determined by sclk. sid is in a dont care state when no data is being clocked in. smode - serial interface mode, pin 24. selects the operating mode of the serial port. when low the serial port operates in the 5 or 4 wire interface mode. when high the chip will enter the 3 wire interface mode. analog inputs ain+ and ain- - analog inputs, pins 6, 7. the analog input signals from the transducer. these are true differential inputs. vref+ and vref- - voltage reference inputs, pins 9,10. these are the differential analog reference voltage inputs. mdrv+ - modulator differential voltage reference, pin 1. positive terminal of the internal differential voltage reference which can be tied to the positive supply (va+) or ground (agnd). mdrv- - modulator differential voltage reference, pin 2. this is the -3.75v modulator differential voltage reference output and can be used to generate an analog reference. note this is with reference to the mdrv+ pin. cs5516, cs5520 28 ds74f1 28 ds74f2
digital outputs bx1 and bx2 - ac bridge excitation signals, pins 12, 11. these can be buffered to drive the transducer or used as synchronizing signals for a transducer drive circuit. bx1 and bx2 are 0 to +5v signals. drdy - data ready, pin 15. drdy goes low every 81,920 cycles of xin (when in read conversion data mode) to indicate that new data has been placed in the output port. drdy goes high when all the serial port data is clocked out, when the serial port is being updated with new data, when a calibration is in progress, or when the device is in sleep. sod - serial output data, pin 18. data from the serial port will be output from this pin at a rate determined by sclk . the data will either be conversion data, or, calibration values, dependent upon the command word that has been previously input on the sid pin. the sod pin furnishes a high impedance output state when not transmitting data (smode = 0). ordering guide model number linearity error (max) temperature range package cs5516-ap 0.003% -40 c to +85 c 24-pin 0.3" plastic dip cs5516-as 0.003% -40 c to +85 c 24-pin 0.3" soic CS5520-BP 0.0015% -40 c to +85 c 24-pin 0.3" plastic dip cs5520-bs 0.0015% -40 c to +85 c 24-pin 0.3" soic cs5516, cs5520 ds74f1 29 ds74f2 29 ordering information environmental, manufacturi ng, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. model package resolution liearity error channels temperature cs5516-ap 24-pin plastic dip 16 bits 0.0030% 4 -40 to +85 c cs5516-as 24-pin soic cs5516-asz (lead free) CS5520-BP 24-pin plastic dip 20 bits 0.0015% cs5520-bs 24-pin soic cs5520-bsz (lead free) model number peak reflow temp msl rating* max floor life cs5516-ap 260 c 1 no limit cs5516-as 240 c 2 365 days cs5516-asz (lead free) 260 c 3 7 days CS5520-BP 260 c 1 no limit cs5520-bs 240 c 2 365 days cs5520-bsz (lead free) 260 c 3 7 days
specification definitions linearity error the deviation of a code from a straight line which extends between two fixed points on the a/d converter transfer function. in unipolar mode, the straight line extends from one point located 1 2 lsb below the first code transition, one count above all zeros; to the second point located 1 2 lsb beyond the code transition to all ones. in bipolar mode, the straight line extends from one point located 1 2 lsb beyond the code transition to all ones, passing through a point 1 2 lsb below code 8000(h) (16-bit); 80000(h) (20-bit); extending to beyond negative full scale. units are in percent of full-scale. differential nonlinearity the deviation of a codes width from the ideal width. units in lsbs. full scale error the deviation of the last code transition form the ideal [{(vref+)-(vref-)}- 3 2 lsb]. units are in lsbs. unipolar offset the deviation of the first code transition from the ideal ( 1 2 lsb above agnd) when in unipolar mode (bp/ up low). units are in lsbs. bipolar offset the deviation of the mid-scale transition (011...111 to 100...000) from the ideal ( 1 2 lsb below agnd) when in bipolar mode (bp/ up high). units are in lsbs. cs5516, cs5520 30 ds74f1 30 ds74f2 contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in aircraft systems, military applications, products s urgically implanted into the body, automotive safety or security de- vices, life support products or other critical applic ations. inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer uses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.
31 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb5516 cdb5520 cs5516 and cs5520 adc evaluation board features l on-board microcontroller l rs232 serial communicationswith host pc l supports either ac or dc bridge drive l on-board bridge driver l supports ratiometric or absolute measurements l evaluation software included description the cdb5516 and cdb5520 provide quick and easy evaluation of the cs5516 and cs5520 bridge transducer a/d converters. direct connection of the bridge to the evaluation board is provided. the board also contains a microcontroller, with firmware which allows the board to be controlled via simple serial commands, using the rs232 communications port of a pc. ordering information cdb5516 evaluation board cdb5520 evaluation board i vref+ vref- ain+ ain- clock microcontroller rs232 driver/ receiver rs232 connector bx1 bx2 +5v 0v -5v +5v 0v cs5516 cs5520 sclk sid sod load cell bridge excitation mar 95 ds74db# copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cdb5516 cdb5520 cs5516 & cs5520 adc evaluation boards sep ?05 ds74db4
introduction the cdb5516/20 evaluation board provides a means of testing the cs5516 and cs5520 bridge transducer a/d converters. the board is de- signed to be interfaced to a pc-compatible computer via an rs-232 port. software is sup- plied with the board which provides control of all registers in the cs5516 or the cs5520. the board is configured to be operated from +5 and -5 volt power supplies. a bridge transducer or a bridge transducer simulator is required if the board is to be evaluated in the ratiometric oper- ating mode. evaluation board overview figure 1 illustrates the schematic of the bridge driver and a/d converter portion of the circuit board. the converter operates from a 4 mhz crystal. this results in the converter outputting conversion words at a 50 sps rate. the board comes configured to be interfaced to a bridge transducer via the 6-pin transducer terminal block. the sense lines on the transducer termi- nal block provide the reference voltage for the converter. for absolute measurements, the user can connect either an external reference voltage (up to 3.8 volts) to the reference terminal block or connect the on-board 2.5 volt lt1019 reference as the voltage reference for the converter. 10k 10k -5va 3 5 4 6 2 7 0.1 m f 10 m f + +5va 301 301 4.7nf 4.7nf 470pf 470pf 1a 1b 2a 2b micrel mic4428 exc exc u3 c20 c21 r14 r15 q1 tp0610 r12 r11 c18 c19 lt1019- 2.5v +5va 5.0k r6 7.5k r5 7.5k r7 50 0.1 m f r8 c29 c14 0.1 m f vd+ bx1 xin xout smode sod sid sclk dgnd vd- cs 0.1 m f 10k 23 osclk 24 18 17 16 15 14 13 19 va+ mdrv+ mdrv- 1 m f 10 1 2 3 20 0.1 m f +5va bx2 va- 4 21 10 dgnd agnd -5va ain+ agnd1 agnd2 ain- vref+ vref- 6 5 8 11 100k cs5516/20 7 9 10 12 22 100k 4.000 mhz r13 c7 c9 r1 r17 r16 c8 smode sod sid sclk cs rst drdy smode sod sid sclk rst cs drdy drdy rst j1 0.1 m f c11 0.1 m f c10 sig+ sig- sense+ sense- exc+ exc- p1 4.7nf c15 ref+ ref- 301 301 p2 r4 r3 to figure 2 r2 exc gnd c16 c17 u5 figure 1. bridge driver and a/d converter cdb5516/cdb5520 32 ds74db3 32 ds74db4
a bridge driver, composed of a siliconix tp0610 transistor and a micrel mic4428 dual cmos driver, is provided which allows the bx2 output from the cs5516 or cs5520 to provide either dc or ac excitation to the bridge. the digital interface pins of the a/d converter connect to the microcontroller, or alternatively, these connections can be cut, or the on-board microcontroller can be removed, and the users own microcontroller can be interfaced to j1 header connector. figure 2 illustrates the motorola 68hc705c8 microcontroller which reads or writes data into the a/d converter and communicates with the pc-compatible computer via the rs-232 inter- face. the microcontroller derives its 4 mhz clock from the a/d converter clock. the micro- controller is configured to communicate over the rs-232 link at 4800 baud, no parity, 8-bit data, and 1 stop bit. a motorola mc145407 rs-232 interface chip is used to send and recieve data to the pc-compatible computer via the 25-pin sub- d connector. table 1 lists the commands sent to the microcon- troller to write to or to read from the registers in the a/d converter. if software other than that provided with the evaluation board is used, the format of the data transmitted over the rs232 line is as follow: write commands are com- vpp osc2 osc1 pa1 pd2 pd4 pd7 pa0 pa2 v dd pb7 19 pb6 18 pb5 17 pb4 16 pb3 15 pb2 14 pb1 13 pb0 12 38 39 10 31 32 33 36 11 9 pd3 + 47 m f 0.1 m f reset irq pd0 pd1 pc7 21 pc6 22 pc5 23 pc4 24 pc3 25 pc2 26 pc1 27 pc0 28 pa7 4 pa6 5 pa5 6 pa4 7 pa3 8 tcap 37 tcmp 35 pd5 34 2 29 30 reset 10k 1 m f 1 +5vd 10k 3 470 vss 20 40 68hc705c8 10k u2 c24 470 r20 c23 c22 d1 smode sod sclk drdy osclk sid cs rst from figure 1 470 d2 +5vd ri txd rxd rts cts dtr dsr dcd 22 2 3 4 5 20 6 8 7 10k 10 m f 18 20 5 6 7 8 9 10 11 12 13 14 15 16 1 3 19 17 10 m f + + + vcc c2+ v dd c2- +5vd + gnd vss 2 4 c1+ c1- sub-d 25 pin c28 c27 r28 u4 mc145407 10 m f c25 10 m f c26 rxd txd figure 2. microcontroller and rs-232 interface cdb5516/cdb5520 ds74db3 33 ds74db4 33
posed of one byte for command which is trans- mitted with its lsb first. the command is followed by three data bytes which make up the 24-bit word to be written to the selected register of the a/d converter. the three bytes are trans- mitted lowest order byte first (bits 7 - 0) with the lsb of the byte transmitted first. figure 3 illustrates the power supply connections to the evaluation board. voltages of +5 and -5 analog and +5 digital are required. using the evaluation board prior to using the board to evaluate the cs5516 or cs5520 a/d converter, a good understanding of the full potential of the converter is necessary. it is recommended that the cs5516/cs5520 de- vice data sheet be thoroughly read prior to attempting to use the evaluation board. the cs5516 or cs5520 bridge transducer a/d converter actually contains two a/d converters. one of the converters is used to convert the vref voltage input, and the other is used to convert the ain signal input. both converters utilize an on-chip voltage reference to perform conversions of their respective inputs. since both converters use the same reference they track one another. the digital processing logic of the a/d converter depends on the presence of both signals to properly compute a digital output word. if the evaluation board is configured for bridge measurement, and no bridge (load cell or simulator) is connected to the bridge transducer terminal block, the converter will output a code of zero because no reference voltage is present between the vref+ and vref- pins. the span of the ain input signal is determined by a combination of the instrumentation ampli- fier gain (x25), the programmable gain amplifier (pga) gain, the magnitude of the voltage be- tween the vref+ and vref- input pins, and the calibration words for gain and offset. for ex- register read write conversion data register 50(h) configuration register 51(h) d1(h) dac register 53(h) d3(h) gain register 52(h) d2(h) ain ratiometric offset register 54(h) d4(h) ain nonratiometric offset register 55(h) d5(h) vref nonratiometric offset register 56(h) d6(h) table 1. microcontroller commands via rs-232 +5vd 0.1 m f + 47 m f +5 +5va 0.1 m f + 47 m f 0.1 m f + 47 m f -5va -5v +5v z1 z2 c3 c1 c4 c2 z3 c5 c6 agnd dgnd figure 3. power supplies cdb5516/cdb5520 34 ds74db3 34 ds74db4
ample, the board comes with a set of precision resistors which divide the excitation supply (nominally 10 volts total) down to 2.5 volts be- tween the vref+ and vref- input pins. this sets the nominal full scale voltage into the a/d converter. the input span of the instrumentation amplifier can be calculated to by knowing the pga gain setting, and that the gain of the instru- mentation amplifier is x25. if the pga is set for a gain of 8, then the input span to the instrumen- tation amplifier will be 2.5 volts (vref+ - vref-) divided by 8 x 25, or 2.5/(200) = 12.5 millivolt nominal in unipolar mode. the device can be then calibrated with an input voltage which is as low as 20% less than nominal or up to 20% greater than nominal. therefore, with this vref+ - vref- voltage (2.5 volts) and a pga gain of 8 the input span can be calibrated to handle a span from a low of 10 mv to a high of 15 mv. to modify the input span the user can either change the pga gain or modify the resis- tor divider on the bridge sense voltage to yield an appropriate value in the range of 2.0 to 3.8 volts. this makes the a/d converter quite flex- ible in handling load cells with different output levels. whenever configured as a bridge transducer device, the cs5516 or the cs5520 a/d converter operates in ratiometric measure- ment mode. figures 4 and 5 illustrate how to connect 4-wire and 6-wire bridge transducers to the board. alternatively, the cs5516 or cs5520 can be configured for absolute measurement if a preci- sion reference voltage is supplied between the vref+ and vref- pins of the a/d converter. the board can be modified to accept a reference into the voltage reference terminal block; or the on-board lt1019-2.5 volt reference can be used as the reference voltage for the a/d converter. to use either of these inputs will require that jumper wires be soldered in either 1a-1b to se- lect the external voltage reference input, or 2a-2b to select the on-board lt1019-2.5. fig- ure 6 illustrates the connection of an external voltage reference to the evaluation board for ab- solute voltage measurement applications. to achieve an accurate reference voltage resistor r6 sig + sig - sense + sense - exc + exc - + _ figure 4. 4-wire bridge connections sig + sig - sense + sense - exc + exc - + _ figure 5. 6-wire bridge connections cdb5516/cdb5520 ds74db3 35 ds74db4 35
must be removed from between the +vref and -vref pins. it may be desirable to also remove r5, r7, c16, and c17 in some applications. calibrating the a/d converter as explained in the cs5516/cs5520 data sheet, the order in which the calibration steps are per- formed are important. if one chooses to use the non-ratiometric calibration capabilities of the converter, the non-ratiometric errors of the vref and ain channels should be calibrated first. the non-ratiometric calibration steps can be performed at the same time. before the non- ratiometric offset calibration is initiated, the bridge should be grounded. this can be achieved on the evaluation board by moving the two jumpers at the output of the mic4428 driver to the gnd position (see figure 1). the converter is then instructed via the configuration register bits to perform the non-ratiometric calibration steps. once the non-ratiometric calibrations are completed, jumpers at the output of the mic4428 driver should be returned to the exc position. after the non-ratiometric calibration steps are performed, the ain ratiometric offset is then calibrated. with "zero weight" on the load cell, the converter is instructed via the configuration register to perform the ain ratiometric offset calibration step. finally, with "full scale weight" on the load cell, the converter is instructed to perform the gain calibration step. the converter is then ready to perform conver- sions. software the evaluation board comes with software and a rs-232 cable to interface the board to a rs-232 port of a pc-compatible computer. the software diskette contains a readme.txt file which explains its operation. +5vd 0.1 m f + 47 m f +5 +5va 0.1 m f + 47 m f 0.1 m f + 47 m f -5va -5v +5v z1 z2 c3 c1 c4 c2 z3 c5 c6 agnd dgnd figure 6. using off-board voltage reference cdb5516/cdb5520 36 ds74db3 36 ds74db4
figure 7 illustrates the software supplied with the cdb5516/cdb5520 evaluation board. the software allows the user to manipulate the regis- ters of the converter and perform calibrations and conversions. it decodes the status of the con- figuration register and indicates the gain register scale factor. the software enables the user to collect data to a file, average samples and com- pute the average and standard deviation of the samples which have been collected. figure 7. screen for the cdb5516/cdb5520 evaluation board software cdb5516/cdb5520 ds74db3 37 ds74db4 37
figure 8. cdb5520 silkscreen cdb5516/cdb5520 38 ds74db3 38 ds74db4
figure 9. cdb5520 top ground plane cdb5516/cdb5520 ds74db3 39 ds74db4 39
figure 10. cdb5520 solder side trace layer cdb5516/cdb5520 40 ds74db3 40 ds74db4
ds74db4 41 contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into the body, au tomotive safety or security de- vices, life support products or other critical applic ations. inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer uses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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